1. Field of the Invention
The present invention relates to a duty cycle correction device used in a semiconductor memory chip, and more particularly to a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) device by using a phase mixer.
2. Description of the Prior Art
As generally known in the art, a DLL device is a clock generating device, which is accommodated in a synchronous memory device so as to compensate for skew between an external clock and an internal clock. Synchronous memory devices, such as DDR, DDR2, etc., control the timing for input/output operations in synchronization with an internal clock output from a DLL device. In the case of these synchronous memory devices, since data are input/output in synchronization with the rising and falling edges of an external clock, it is preferred that the duty cycle of an internal clock output from a DLL device is set as 50% if possible. Therefore, in order to adjust the duty cycle of an internal clock output from the DLL device to be approximately 50%, a duty cycle correction (DCC) device employing a delay circuit or the like is typically used.
However, the conventional DCC device, which employs a delay circuit or the like in order to adjust the duty cycle of an internal clock output from a DLL device, has a problem in that the correcting ability for the duty cycle is very poor.